1. Field of the Invention
The present invention relates to the testing of integrated circuits and especially to the testing of EEPROM cells.
2. Discussion of the Related Art
Many electronic circuits use EEPROM cells to temporarily store data. FIG. 1 shows a simplified diagram of an EEPROM cell 10, which includes an N-channel MOS transistor 12, the source 13xe2x80x2 of which is connected to the drain 13xe2x80x3 of a floating gate MOS transistor 14. When several cells 10 are arranged in an array, drain 16 and gate 18 of a transistor 12 are, for example, respectively connected to a bit line and to a word line. The source of transistor 14 is connected to a reference terminal 20. Control gate 22 is connected to a control line 23. The floating gate is designated by reference 24.
FIGS. 2A and 2B respectively show a top view and a cross-section view of an embodiment of an EEPROM cell 10. Same references designate same elements as in FIG. 1. Cell 10 is formed on a lightly-doped P-type substrate 11. The gate of transistor 12, made of polysilicon, extends above an area separating two N-type doped regions, forming drain 16 and source 13xe2x80x2 of transistor 12. Gate 18 is separated from substrate 11 by silicon oxide 11xe2x80x2. Floating gate 24 of transistor 14, made of polysilicon, includes a main portion which extends above a heavily-doped N-type region forming control gate 22. The main portion of the floating gate is separated from area 22 by an oxide 22xe2x80x2. Floating gate 24 further includes two doped regions forming drain 13xe2x80x3 and source 20 of transistor 14. A second finger extends above a heavily-doped N-type region 25, connected to drain 13xe2x80x3. A thin oxide area 26 is located between the second finger of floating gate 24 and region 25, which forms a tunnel capacitor C2 between drain 13xe2x80x3 and floating gate 24. The writing of data into cell 10 corresponds to the injection of charges into floating gate 24 through tunnel capacitor C2 by the Fowler-Nordheim effect. The operation of cell 10 is, conventional and will not be further described herein.
FIG. 3 schematically shows a portion of a semiconductor wafer on which several chips 27, each including a great number of EEPROM cells 10, have been manufactured. Chips 27 are separated by chip cutting areas. It is important, before selling each of chips 27, to test the quality of all its EEPROM cells 10. In particular, the quality and aging stability of all tunnel capacitors C2 of EEPROM cells 10 is desired to be tested. Indeed, the oxide of the tunnel capacitors is very thin and its quality is critical for the cell operation. If, for any reason, for example, poor manufacturing, the tunnel oxide of at least one of capacitors C2 of a cell 10 of a circuit 11 is defective, the oxide can be punctured and develop a short-circuit after several write and read operations, and make circuit 27 non-functional. A conventional method to test the proper aging of all tunnel capacitors C2 consists of performing a great number of write and read operations in each of cells 10. This type of testing is extremely expensive and it can damage the tested structures. Another method consists of making test cells identical to the memory cells and of testing the aging thereon. However, if the number of test cells is limited, the obtained results may not be reliable. Indeed, if the probability of the defect is small, the analysis of the performances of a small number of test cells is insufficient to predict the performance of a great number of memory cells. It is possible to increase the value of this test by increasing the number of test cells, but the space taken by the test cells becomes significant, which is expensive. It thus appears to be impossible to perform a testing which properly reflects the quality of the tunnel oxide of all the floating gate transistors of an EEPROM memory of a chip.
An object of the present invention is to provide a test cell that provides a reliable indication of the quality of all the EEPROM cells of a chip.
Another object of the present invention is to provide such a test cell which can be implemented without increasing the size of the chip and without any additional cost.
To achieve these and other objects, the present invention provides a testing circuit made on a silicon wafer including a plurality of identical cells, each of which includes a primary capacitor of given characteristics, which includes a test capacitor of same characteristics as each primary capacitor and of surface at least equal to the sum of the surfaces of the primary capacitors.
According to an embodiment of the present invention, each cell includes several primary capacitors of distinct types, and the testing circuit includes a number of test capacitors equal to the number of primary capacitors of each cell, each test capacitor having the same characteristics as the primary capacitors of a given type, the test capacitors being interconnected like the primary capacitors.
According to an embodiment of the present invention, the testing circuit is formed on a wafer, the cells of which are EEPROM cells, each including three primary capacitors corresponding to a capacitor between the floating gates and of control series-connected with a tunnel capacitor, itself connected in parallel with a capacitor between the floating gate and the substrate, and which includes three test capacitors.
According to an embodiment of the present invention, the testing circuit is located on an area of the wafer in which a separation cutting of the chips is performed.
According to an embodiment of the present invention, the testing circuit is reproduced several times on the wafer according to a homogeneous distribution.
The foregoing as well as other objects, features and advantages of the present invention will be discussed in detail in the following non-limiting description of an embodiment-of the present invention in connection with the accompanying drawings.